HI5746EVAL1【PDF 1/16 页】EVALUATION PLATFORM HI5746

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Using the HI5746EVAL1 Evaluation Board

Application Note

February 1999

AN9725.2

Description

The HI5746EVAL1 evaluation board for the HI5746 can be

used to evaluate the performance of the HI5746 10-bit

40MSPS analog-to-digital converter (ADC). As shown in the

Evaluation Board Functional Block Diagram, this evaluation

board includes sample clock driver circuitry, reference

voltage generators and single-ended to differential analog

input drive circuitry. Buffered digital data outputs are

conveniently provided for easy interfacing to a ribbon

connector or logic probes. The evaluation board is provided

with some prototyping area for the addition of user designed

custom interfaces or circuits.

HI5746 A/D Theory of Operation

The HI5746 is a 10-bit fully differential sampling pipeline A/D

converter with digital error correction logic. Figure 1 depicts

the circuit for the front end differential-in-differential-out

sample-and-hold (S/H). The switches are controlled by an

internal sampling clock which is a non-overlapping two

phase signal , Φ 1 and Φ 2 , derived from the master sampling

clock. During the sampling phase, Φ 1 , the input signal is

applied to the sampling capacitors, C S . At the same time the

holding capacitors, C H , are discharged to analog ground. At

the falling edge of Φ 1 the input signal is sampled on the

bottom plates of the sampling capacitors. In the next clock

Evaluation Board Functional Block Diagram

phase, Φ 2 , the two bottom plates of the sampling capacitors

are connected together and the holding capacitors are

switched to the op-amp output nodes. The charge then

redistributes between C S and C H completing one sample-

and-hold cycle. The front end sample-and-hold output is a

fully-differential, sampled-data representation of the analog

input. The circuit not only performs the sample-and-hold

function but will also convert a single-ended input to a fully-

differential output for the converter core. During the sampling

phase, the V IN pins see only the on-resistance of a switch

and C S . The relatively small values of these components

result in a typical full power input bandwidth of 250MHz for

the converter.

As illustrated in the HI5746 functional block diagram and the

timing diagram in Figure 2, eight identical pipeline

subconverter stages, each containing a two-bit ?ash

converter and a two-bit multiplying digital-to-analog

converter, follow the S/H circuit with the ninth stage being a

two bit ?ash converter. Each converter stage in the pipeline

will be sampling in one phase and amplifying in the other

clock phase. Each individual subconverter clock signal is

offset by 180 degrees from the previous stage clock signal

resulting in alternate stages in the pipeline performing the

same operation.

SAMPLE

CLOCK

INPUT

50 ?

+5V D

BIAS

TEE

CLK

CLOCK

OUT

1.2V

BANDGAP

VOLTAGE

REFERENCE

VAR

GAIN

VAR

GAIN

+2.5V

+2.0V

CLK

V REF +

V REF -

CLK

ANALOG

INPUT

G = +1

V IN +

D 0 -D 9

DIGITAL

DATA

OUT

DGND

AGND

50 ?

G = -1

V IN -

HI5746

(D0 - D9)

+5V D

+5V A

-5V A

3-1

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Corporation.

? Intersil Corporation 2000

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